The present application relates generally to an improved data processing apparatus and method and more specifically to mechanisms for dynamic inclusive policy in a hybrid cache hierarchy using bandwidth.
A central processing unit (CPU) cache is used to reduce memory latency. Modern processors use multiple levels of cache hierarchy, where higher level caches, such as level 1 (L1) cache, are closer to the processor core, while tower level caches, such as level 2 (L2), level 3 (L3), or the like, are further away from the processor core. In multi-level cache hierarchies, a cache may be classified as inclusive or exclusive, where inclusive means a cache comprises all data of any higher level cache in the cache hierarchy and exclusive means that data is only present in one cache of the cache hierarchy.
Given a fixed cache size for the higher and lower level caches, an exclusive multi-level cache hierarchy approach has a higher cache hit rate than an inclusive multi-level cache hierarchy approach due to the fact that the total cache capacity between the cache levels is greater in the exclusive approach than the inclusive approach if both hierarchies are the same size, the exclusive approach has twice the capacity of the inclusive approach.